Computer systems rely on efficient communication to transfer data, instructions, and status signals between devices. The multilayer bus, such as the Multilayer AHB® available from ARM of Cambridge, England, is a well-known communication medium. It forms a matrix of connections between its input ports, which are attached to masters, and its output ports, which are attached to slaves. The connection matrix allows any given master to access any slave.
A common optimization in multilayer systems is to introduce a split capability in some, if not all, of the connected devices. In order for the split capability to be beneficial, both the master and the slave in a given transaction must be split capable. Assuming this is the case, an illustrative split transaction proceeds as follows.
Suppose a master needs to read data from a peripheral slave. A master may be a microprocessor, controller, state machine, or any appropriate circuitry. The master will issue a read request to the slave, using the bus matrix described above. The slave will receive this request and, assuming the data is not yet ready for transmission, will issue a split response to the master. When the master receives the split response, it will release the slave bus. At this point, both the master and the slave are temporarily freed from the transaction. The master can perform other tasks while waiting for the data, and the slave can communicate with other masters. When the slave is finally ready to transmit the requested data, it will send an unsplit signal to the master, which will in turn issue a second read transaction and retrieve the desired data.
The split optimization described above is especially beneficial when slaves typically produce data with high latency. Without the use of splits, the slave bus would be tied up while the slave retrieves and prepares the data. This holding of the slave bus reduces the efficiency of the devices involved, as well as system efficiency as a whole.
However, a problem arises when a master without split capability tries to communicate with a split capable slave. When this occurs, the slave will issue a split response to the master, but the master will not understand the response. As a result, the master may keep retrying the same read request, or it may simply hang. In either case, both the master and the slave are rendered inactive until the transaction is aborted.
One obvious solution to this problem would be to make all masters split capable. Since split capable masters are able to interact with both split capable slaves and slaves without split capability, all masters would then be able to communicate with all slaves. Unfortunately, there are at least two problems with this solution. First, some masters must wait for the requested data to arrive from the slave before performing other tasks. Making such masters split capable would only add a 3-cycle overhead for each read transaction (one cycle for the split response, one for the unsplit signal, and one for the subsequent read request), thereby reducing its performance with split capable slaves. Second, it is not always possible to make a master split capable. For instance, the master may be an off-the-shelf processor that cannot be modified to accommodate splits.
In view of the foregoing, it would be desirable to find a way for masters without split capability to communicate with split capable slaves. Ideally, the solution would involve little change to the masters and slaves themselves.